To the dismay of skeptics, Moore’s law has held true for 60 years. The number of transistors per microchip has roughly doubled every two years, but the cost of adding transistors has increased exponentially—not linearly. Additionally, more transistors in a smaller area generate new manufacturing and engineering challenges. As transistor counts exploded, silicon wafer quality became more critical. Crystal lattice defects, dopant concentration variations, and surface contamination can disable circuit pathways and create entire regions of non-functional transistors. Put simply, silicon defects are extremely expensive problems that are much more likely to occur on larger dies for monolithic system-on-chips (SoCs). To combat the risks associated with packing transistors onto a large die, semiconductor companies have focused research dollars on chiplets, which feature interlocking sets of discrete components on separate pieces of silicon, enabling modular customization that addresses the unique performance and I/O needs of industries such as automotive and medical.